Everything you wanted to know about the development and production of chips, but were afraid to ask

the Lord! I already wrote about upcoming seminars Charles Daneka containing the complete educational program for all stages of design and production chips, but since having add-ons:

* First, to seminars, joined Cadence Design Systems, one of the two leading companies in automation of design of chips. Cadence will present a one-hour report with the program at the end of this post.

Check (UPD: apparently, the original check was exhausted. But romanovtsy said that if the first room is full, they will allocate a bigger place. Write an email to mail).

* Second, the workshops were joined by four leading Russian companies-designers of circuits: JSC "niim "Progress", JSC "BAIKAL ELECTRONICS", LLC "LABSYSTEMS" and JSC SPC "ELVIS". Each of them will make a public presentation with the information you in other circumstances usually will not be able to get without NDA.

* Third, in addition to the official program of seminars in Moscow, St. Petersburg and Kiev, we decided to organize an informal meeting of investigators in the form of walking, first in Moscow this Sunday, October 30. You will be able to show Charles Daneko Moscow (it was the first time in Russia) and to ask about designing chips.

We are thinking that next year to expand such activities in the region of Novosibirsk-Tomsk, therefore here is a welcome video with a girl from Novosibirsk Akademgorodok:

Explanation: RUSNANO and Misa is organizing a workshop Nanometer ASIC in Moscow but in St. Petersburg the seminar is organised by the University ITMO, and in Kiev — KPI, Kyiv national Taras Shevchenko University, laboratory "Lamp" KPI and student workspace "Protein" KPI.

Details about the meeting and workshops — under the cut:

The format of the informal meeting will be the same as the format like last year's meeting (which really was no Charles Danika). Meet at 12 noon Sunday October 30, exit metro Smolenskaya blue line of the subway (the tradition of the rendezvous we used MIFI-schnick). After that we go to 15.00 lunch in Jean-Jacque on Nikitsky Boulevard to reposition Jean-Jacques from the meeting point creative Humanities at the meeting place of harsh engineers the microelectronics industry.

If you are late, call me (Yuri Panchul) +7 925 022 5427



Information on the seminar "Specialized integrated circuits of the nanoscale"

The seminar introduces students to the gradual development of integrated circuit (hereinafter ASIC) technology of the nanoscale (32 nm and below).

Information about the lecturer: Charles Danek (Charles Dancak)

International expert, Professor University of California, Santa Cruz in Silicon Valley, engineer is the administrative apparatus of Synopsys for over 10 years.

Received a MSEE at the University of Wisconsin (Madison) and a master's degree in the field of solid state physics at the Polytechnic Institute of new York (Brooklyn). Taught in eight countries. Worked in companies Teradyne, Cadence and Silicon Compilers.

The seminar will address the following questions:

PHASE 1: SPECIFICATION

• The principles of elements AND and OR NOT, the topology of the standard cells suitable for synthesis.
• Specification CMOS chip like product on the paper: table of characteristics; feasibility study; cost of the chip.
• Business ecosystem ASIC without its own manufacturing facilities (fabless); options technological process; plates for Shuttle launches; other key components of planning.

STEP 2: PRACTICAL DESIGN

• Example: writing RTL code for simple digital functions in SystemVerilog.
• How tools VLSI synthesis converts RTL description to an optimized schematic of the standard cell.
• Calculation of the delay at the logical level, based on data from the standard cell library and estimated values of the lengths of the chains.
• Synthesis of RTL code into the logic that is specific to the particular technology. The imposition of restrictions on the period clock.
• The temporal characteristics of one cycle of the clock signal: can new data to go through the critical path within one cycle.
• Writing RTL assertions by analogy with binary reviews that are verified by means of simulation or by means of FEC (formal verification).

the sub-section: Design based on IP-blocks

• Formats of IP-blocks: programmatic (synthesized), hardware (reprogrammable), is topologically rigid. How the format affects the price.
• Types of IP-blocks: Central processing unit (CPU), processor, digital signal processing (DSP), graphics processor (GPU), a processing unit of the signals (RPU), cryptography, digital interfaces, analog circuit.
• Classes of IP blocks, CPU blocks, entry-level MCU and IoT, middle level for efficient embedded systems, high-performance level. Multi-core blocks; homogeneous and heterogeneous calculations.
• Bus and network-on-chip. The use of front-end language constructs in SystemVerilog in order to encapsulate the busbar joints with concise and reusable encoding.

the Subkey: RF/analog design

• Standard design for on-chip RF/wireless design, immune to variations of process.
• Example: design of a voltage controlled oscillator (VCO), to topology GDSII.
• Writing Verilog-AMS models of the VCO to detect mistakes, such as wrong polarity or crossed signals.

STEP 3: FUNCTIONAL VALIDATION

• The evolution of the test bench: simple bench block-level to multi-level bench system that uses transactions; restricted random effects (CRV); built-in assertions SystemVerilog; criterion functional coverage.
• Formal verification of equivalence to confirm: the functionality will not change after the introduction of scan chains, the introduction of the clock signal and changes to manual mode (ECOs).
• Emulation on the hardware: build hardware model based on FPGA, which is ideal for early debugging for the developed, but not yet produced, chip.

STEP 4: IMPLEMENTATION

• Synthesis of verified RTL source code, the satisfaction of temporal requirements, constraints of the area, etc.
• The processing clock signal during the logic synthesis and physical design. Convergence domains of the signals.
• Breaking time characteristics. Remediation methods. The calculation of the delay elements and circuits.
• Physical design phases: topological planning, standard cell placement, clock tree synthesis signal tracing.
• Preparation of crystal production: wiring, power supply, elimination of congestion or excessive voltage drop (IR drop), checking design rules (DRC).

the sub-section: Design for testing

• Insert scan chain of the system, generation of test patterns for detecting faults of type constant circuits (bridging) and error latency.
• Built-in self-test for memory (MBIST) and logic blocks (and LBIST STUMPS).
• Organization of the boundary-scan along the periphery of the chip for testing on the level of the boards.

the sub-section: transfer of production

• What are the causes of violation of the integrity of signals, such cross-interference?
• Verification topology and schematics (LVS) in order to confirm the compliance of the topology to a circuit description.br> • General GDSII file, geometric description attractivenes topology of the whole crystal.
• Download GDSII file for manufacturing masks. Prepare to build mask (OPC).

STEP 5: PRODUCTION

• As a database, a GDSII file is used to create an accurate set of masks or reticles. What limits the resolution?
• Basic fabrication techniques: photolithography, oxidation, ion implantation, metallization, IMD, CMP.
• As an innovative design, this dual lithography, ensure the fulfillment of Moore's law in the present and the future.

the Subkey: FEOL manufacturing (the application of semiconductor structures)

• Isolation of small grooves (Shallow trench isolation) – the secret to cost-efficient processing of CMOS wafers.
• The formation of the gate polysilicon (including HKMG) and implantation of the drain/source.
• Making complementary transistors n and p – type bases of the inverter.

the Subkey: BEOL manufacturing (deposition of metal)

• How to apply the Metal layer 1 by applying a copper pattern (copper damascene processing).
• Isolating each metal layer from the following (IMD), the formation of contact/transition interlayer connections.
• Banirovonii wafers designed for flip-chip housing are demonstrated. Wire-bond (razborka wire).
• Grading sheets of the test to identify the suitable crystals for housing are demonstrated.

STEP 6: the CULLING

Packing crystal using flip-chip or wire-bond testing, testing for minimum performance, and culling for use in the system of the customer throughout the working life of the product. Includes:

the sub-section: Engineering design and Assembly

• Joint development of the body: electrical, thermal, and mechanical considerations.
• Technology flip-chip and wire-bonding.
• Flow signal out of the crystal via the metal layers, the RDL layer, bumpy, the output PC Board. Modeling of the influence of the body.
• Silicon vias and 3D of the housing are demonstrated.

the sub-section: Testing and Diagnosis

• Within ATE: As a test vector detects a single constant mistake of the millions on the chip.
• Shmoo plots (text-graphical diagrams); analysis of the operation of the chip in a technologically boundary conditions.
• Functional testing the frequency range; measuring fmax Iddq and static.

the sub-section: Inspection of silicon

• Design test Board with a custom (FPGA) hardware to test the device at a desired frequency.
• Use of logic analyzers, logs scan tests, JTAG ports, and often instrumentation on the chip.
• Bug fixes related to patches in masks of metal layers, allowing the use of spare components or triggers.

The workshop will present examples of how the CAD tools are used in real projects of JSC "niim "Progress", JSC "BAIKAL ELECTRONICS", LLC "LABSYSTEMS" and JSC SPC "ELVIS".

the program of the seminar "Specialized integrated circuits of the nanoscale"

Venue: nust "MISIS", main building, room B-636.

the 31.10.16
9.00—9.30 Registration
9.30—9.45 introduction of the speaker
9.45—10.45 Stage 1: Specification

Circuits: basic concepts, historical view, the key open, the switches are n-type and p-type CMOS logic.

10.45—11.00 Break
11.00—12.00 Stage 1: Description of the circuits (continued)

Ecosystem fabless VLSI. The cost of the chip.

12.00—13.00 Stage 2: development

Writing RTL code in SystemVerilog for a simple logic function (serializer, serializer). In netlist synthesis based on standard cells. The delay calculation. Single synchronization cycle. Fix broken synchronization. RTL assertions.
Demo-keys JSC "niim "Progress".

13.00—14.00 Lunch
14.00—15.00 Stage 2: case studies (continued)

[joint presentation with Yuri Panchula, Imagination Technologies]
Subkey: System design on chip (SOC) based on IP cores and buses. The main types of IP cores. Bus and interfaces on the chip.

Demo-keys JSC "BAIKAL ELECTRONICS".

15.00–15.15 Break
15:15-16.00 Stage 2: case studies (continued)
Sub-section: radio frequency (RF)/analog design and simulation.
16.00—17.30 Stage 3: Functional Verification

Evolution of test sets, from basic block level to multi-layered at the system level. Verification of random samples with restrictions (CRV). Monitoring of SystemVerilog assertions. Verification formal equivalence (FEC). Hardware emulation based on FPGA.

17.30—18.00 Results:

Discussion, questions and answers.

18.00—19.00 Thematic presentation of Cadence Design Systems

"Route physical design digital VLSI design using Cadence platform Innovus".

01.11.16

9.00—9.45 Registration and morning coffee
9.45—10.45 Stage 4: Implementation

The final synthesis. The transition from the logical level to the physical. File process: basic layers; the layers of metal; parasitic resistance and capacitance. Basic planning; placement of cells; the synthesis tree synchronization; trace (global and detailed). The solution to the problems of the convergence of the trace task.

Demo case, OOO "LABSYSTEMS".

10.45—11.00 Break
11.00—11.30 Stage 4: Implementation (continued)

Preparation of crystal production: the location of the contact pads; the wiring of power supply; excessive voltage drop (IR drop); DFM; verification of standard and custom design rules.

11.30—12.00 Stage 4: Implementation (continued)

The preparation for the production. The transition from development to production. The final inspection of geometrical and electrical design rules (DRC, ERC). Verification of the topology and schematics (LVS). The creation of the GDSII file.

Demo-keys JSC SPC "ELVIS".

12.00—13.00 Stage 5: Production: the application of semiconductor structures, FEOL,

From GDSII database to a set of masks. The application of semiconductor structures from the database of the project on the crystal layer by layer. Steps initial phase (front-end). Base layers (the semiconductor structure) of the inverter.

13.00—14.00 Lunch
14.00—15.00 Step 5: Production: the application of metal layers, BEOL (continued)

Stack layers of metallization. Copper: why and how? The layers of metallization are not the same. Layer of the redistribution of input-output (RDL — ReDistribution Layer). The steps of the end stage (back-end). Finished circuit of the inverter.

Classifying plates.

15.00—15.15 Break
15.15—16.15 Stage 6: the Culling

Subsection: the Design of the hull and its Assembly. 3-D encapsulation. Testing and testprint. Diagnostic chip for the customer. Shmoo plots (text-graphical charts) and operation of the chip during boundary technological conditions. Statistical fluctuations of the process.

16.15—17.00 Stage 6: the Culling (continued)

Check silicon: the last chance to find mistakes. The technique of error correction, often at the expense of the fixes in the masks of metal layers, which allows the use of spare components or triggers. Issues long-term reliability. The preparation for the production.

17.00—18.00 Totals:

Discussion, questions and answers.

Program from Cadence

Route physical design digital VLSI design using Cadence platform Innovus.

— Familiarity with Innovus
Technology of massive parallelization for increased performance
A new generation of algorithms embed GigaPlace
— An innovative approach to the synthesis of the tree of CCOpt timing
— Improved engine trace NanoRoute
Modern algorithms for multivariate optimization GigaOpt
— Support the most modern technological processes up to 7 nm

— Integration with platform analog design using common database OpenAccess

Two examples of software from Cadence from other workshops and exhibitions:

the 1. Tul for the synthesis of Genus — here's a snippet of his presentation in June at the Design Automation Conference 2015 in San Francisco:

the 2. Simulation and verification. Here is the debug processor cores MIPS microAptiv UP from the package MIPSfpga in the SimVision environment. Name mpc_ on waveform signals is master pipeline control (control of the main conveyor):

Article based on information from habrahabr.ru